1. Field of the Invention
The present invention relates to a printed circuit board design method and apparatus, more specifically a method and apparatus for determining the arrangement of an interlayer connection member.
2. Description of the Related Art
In recent years, with the increasing speed of signal transmission in an electronic apparatus, there have been problems with unnecessary electromagnetic wave (radiation noise) emissions. In order to address such a problem, various designs for suppressing the radiation noise have been implemented in wiring of a printed circuit board in the electronic apparatus and a wiring harness connected to the wiring as well as an enclosure of the electronic apparatus.
As a design technique to suppress such radiation noise, Japanese Patent Application Laid-Open No. 2003-163467 and Japanese Patent Application Laid-Open No. 2007-272342 discuss a technique which devises ideas in arranging interlayer connection members (vias) used in electrically connecting a plurality of conductive layers in the printed circuit board. Japanese Patent Application Laid-Open No. 2003-163467 discusses a technique for calculating the number of vias arranged within a predetermined area of the printed circuit board and informing a user of the calculation result if the number of the arranged vias is smaller than a predetermined number. Further, Japanese Patent Application Laid-Open No. 2003-163467 discusses a technique for detecting whether the vias are arranged at a predetermined interval and informing a user of the detection result if the predetermined interval is not maintained.
Another design technique under development for suppressing the radiation noise is to shorten the length of a return current path of a high-speed signal current. Here, the return current refers to a feedback current of a signal. The return current flows in a power area or a ground (GND) area near a high-speed signal current. Japanese Patent Application Laid-Open No. 2003-163467 discusses a technique for supporting the arrangement of vias which can realize a shorter return current path near the power line wired on a ground layer. Further, Japanese Patent Application Laid-Open No. 2007-272342 discusses a technique to detect a checkpoint for determining whether a layer of a return current of a signal line needs to be changed and to display an area within a predetermined distance from the check point and where vias are not arranged.
According to the techniques discussed in Japanese Patent Application Laid-Open No. 2003-163467 and Japanese Patent Application Laid-Open No. 2007-272342, after the predetermined notification and the display of the area are performed, the user needs to make additional arrangement of the vias to satisfy requirements. At that time, the user is required to visually check and determine possible positions where the vias can be added. However, it takes considerable time to determine the position where vias can be additionally arranged. In addition, a possibility of error and oversight during the determination increases. Further, regarding the return current, the technique discussed in Japanese Patent Application Laid-Open No. 2003-163467 does not consider a return current path near high-speed interconnection vias.